1. Field of the Invention
The present invention relates to a duty clock of a clock, and more particularly, to a duty cycle corrector of an internally generated clock.
2. Description of the Related Art
Since all blocks of a duty cycle corrector can be embodied with digital logic, operation characteristics of the duty cycle corrector with respect to changes in operating temperature, process, and power voltage are superior and a correction to distortion of an input clock duty in a wide range is possible. Since phase information between multi-phase clocks is constantly maintained, an application of the duty cycle corrector to a system needing the multi-phase clock is possible. Also, since the duty information is stored as a digital code value, a quick switch from a ready mode to a normal operation mode is possible.
In an SDRAM (DDR-SDRAM) using both rising edge and falling edge of a clock and circuits such as a MUX/DEMUX for a high speed data transmission, a clock accurately maintaining a 50% duty cycle is a core factor in determining performance of an overall system. Furthermore, in an application such as a pipeline analog-to-digital converter (pipeline-ADC), in addition to correction to accurately maintain the 50% duty cycle, constantly maintaining phase information between multi-phase clocks is also important.
FIGS. 1A and 1B show conventional analog duty cycle correctors used to solve the duty cycle problem. FIG. 1A shows an example of a conventional analog duty cycle corrector. The analog duty cycle corrector includes a duty cycle correction unit 110 and a control voltage generator 120.
The input and output of the duty cycle correction unit 110 and the control voltage generator 120 is a double-input/double-output system having a complementary value. The control voltage generator 120 generates an analog offset voltage proportional to a duty cycle to maintain a clock duty cycle by 50%. The duty cycle correction unit 110 corrects a duty cycle of a clock by receiving the analog offset voltage as a control voltage.
The above method having merits such as a small chip size and a low power consumption has been widely used. However, since the method is characteristically sensitive to a change in temperature, process, and voltage according to the configuration of an analog circuit. Also, the method has a demerit of losing duty cycle correction information in a ready mode in which a power voltage decreases or the operation of an analog circuit portion is discontinued.
Since the inclination of a rising portion and a falling portion of an input clock must be gentle for accurate operation, coercing a duty cycle is with respect to a high speed clock is difficult. Also, during the correction of a clock duty cycle, since both phases of the rising portion and the falling portion of a clock change, phase information of each clock with respect to a multi-phase clock is not maintained.
Thus, according to the above method, the duty cycle of an input clock must be over 40% because a range of an adjustable offset voltage is limited and a range of change of the inclination of the rising portion and the falling portion of the input clock is limited.
FIG. 1B shows another example of the conventional analog duty cycle corrector.
Two voltage controlled delay lines (VCDLs) 130 and 135 and a pulse width detector 150 perform the same function as the duty cycle correction unit 110 of FIG. 1A. The amount of delay of a coarse VCDL 130 is fixed to a value less than 50% of an input clock cycle while the amount of delay of a fine VCDL 135 is adjusted to an output voltage of an op-amp 170. The amount of delay of each VCDL is controlled by a negative feedback loop such that the total amount of delay after passing through the two VCDLs 130 and 135 is 50% of an input clock cycle.
The pulse width detector 150 having a function similar to that of a phase detector of a PLL generates an output clock CLK_OUT having a duty that is corrected using a rising edge of an input clock and a rising edge of a clock passing through the delay lines. Since a rising point of the output clock CLK_OUT is determined by the input clock and a falling point of the output clock CLK_OUT is determined by a delayed clock, the rising edge of the output clock CLK_OUT can maintain information on the input clock during a duty correction process. According to the characteristic in an operation method of the pulse width detector 150, since there must be no section in which two input clock are high at the same time, pulse shapers 140 and 145 generate an output signal having a narrow pulse width.
The duty cycle information of the output clock CLK_OUT can be detected by a frequency-voltage converters (FVCs) 160 and 165 and the op-amp 170. The FVCs 160 and 165 convert high time and low time of a clock to a proportional voltage using a capacitor. By using the two FVCs 160 and 165, the effects of the offset and noise of the op-amp 170 are removed.
The above method is appropriate for an application using the multi-phase clock since only the change point of the falling portion of the clock is controlled. Also, correction to an input duty error of 30%-70% at an input frequency of 19 MHz is possible. However, since the amount of delay is still controlled by using an analog voltage, the method is sensitive to the change in temperature, voltage, and process and the method is difficult to be applied to an application in which a ready mode is needed. Furthermore, since the pulse shapers 140 and 145 are used at an input end of the pulse width detector 150 to decrease the pulse width, the method is difficult to operate at a high frequency.